This invention relates to a vacuum envelope having an electron source incorporated therein, and more particularly to a vacuum envelope with a built-in electron source which is suitable for use for a field emission device (hereinafter also referred to as "FED") and a method for manufacturing the same.
Recently, vacuum microelectronics provided by semiconductor fine-processing techniques have come to notice in the art, which are constructed in such a manner that a cold cathode is incorporated in a vacuum envelope made of glass or the like and vacuum microstructures of a size as small as microns are integrated. The vacuum microelectronics have been applied to research and development of a vacuum envelope with a built-in electron source for an active element, various sensors for detecting magnetism or the like, an image pickup device, an electron beam unit for lithography, a thin-type flat panel display unit or the like.
The thin-type flat panel display unit is constructed so as to arrange a plurality of fine cold cathodes for every picture cell. The fine cold cathodes which have been proposed in the past include those constructed of a field emission cathode, an MIM type electron emission element, a surface conduction type electron emission element, a PN junction type electron emission element and the like. Of the fine cold cathodes proposed, the most typical one is an FED including field emission cathodes, as disclosed in Nikkei Electronics, No. 654 (Jan. 29, 1996), pp 89-98. Field emission is a phenomenon that when an electric field set to be about 10.sup.9 V/m is applied to a surface of a metal material or that of a semiconductor material, a tunnel effect occurs to permit electrons to pass through a barrier, resulting in the electrons being discharged to a vacuum even at a normal temperature. Such electron field cathodes include an electron emission cathode of the Spindt type by way of example.
The MIM type electron emission element is constructed of a lamination structure wherein a metal layer, a thin insulating layer and a thin metal layer are laminated on each other in order. The MIM type electron emission element thus constructed is operated in a manner to apply a voltage between both metal layers to cause electrons to be emitted from the thin metal layer. The electron emission element of the surface conduction type is so constructed that two electrodes and a high-resistance thin film layer are formed on an insulating layer, wherein a voltage is applied between both electrodes to cause electrons to be emitted from the high-resistance thin film layer arranged between both electrodes. The PN junction type electron emission element is constructed so as to utilize avalanche breakdown. Alternatively, it may be constructed so as to apply a voltage to a PN junction in a forward direction to cause electrons injected into a P-layer to be emitted from a surface of the P-layer.
Referring now to FIG. 6, a basic structure of the Spindt type FED is illustrated. In FIG. 6, reference numeral 1 designates a cathode substrate, 2 is an insulating layer, 51 is cathode electrodes, 52 is gate electrodes, 53 is apertures, 54 is an anode substrate, 55 is an anode electrode, A is an anode lead-out wiring, C1 to Cn are cathode lead-out wirings, and G1 to Gm are gate lead-out wirings.
The cathode electrodes 51 are arranged in a stripe-like manner on the cathode substrate 1 and then the insulating layer 2 is deposited all over the cathode substrate 1 including the cathode electrodes 51. Then, the gate electrodes 52 are formed in a stripe-like manner on the insulating layer 2 while extending in a direction perpendicular to the cathode electrodes 51 and in parallel to each other. A plurality of the apertures 53 are formed at each of intersections between the cathode electrodes 51 and the gate electrodes 52 in a manner to commonly pass through the gate electrode 52 and the insulating layer 2 below the gate electrode 52. The apertures 53 each are formed therein with an emitter 57 of a conical shape while being arranged on the cathode electrode 51, as described hereinafter with reference to FIG. 8. A resistive layer may be often formed between the cathode electrodes 51 and the insulating layer 2.
The anode electrode 55 is arranged on a lower surface of the anode substrate 54 made of a transparent glass material or the like. The anode electrode 55 is formed on a lower surface thereof with a phosphor layer (not shown). The Spindt type FED also includes a drive circuit (not shown) which functions to apply an anode voltage through the anode lead-out wiring A to the anode electrode 55, feed an image signal through the cathode lead-out wirings C1 to Cn to the cathode electrodes 51 and feed a drive signal through the gate lead-out wirings G1 to Gm to the gate electrodes 52.
In the Spindt type FED thus constructed, the gate electrodes 52 are scanned in order and the cathode electrodes 51 are fed with an image signal while keeping an anode voltage applied to the anode electrode 55, to thereby permit the emitters arranged in the apertures 53 to emit electrons, which are impinged on the phosphor arranged on the anode electrode 55, resulting in luminescence of the phosphor.
FIG. 7 is a schematic plan view of the Spindt type FED. In FIG. 7, reference numeral 4 designates a seal material and 56 is insulating studs. A plurality of such insulating studs 56 are vertically arranged on the insulating layer 2 to hold the cathode substrate 1 and anode substrate 54 spaced from each other at a predetermined interval therebetween while ensuring that both substrates withstand an atmospheric pressure applied thereto, with the insulating studs 56 being interposed therebetween. Then, the seal material 4 of a low melting point such as seal glass (frit glass) or the like which is arranged between both substrates 1 and 54 is heated to sealedly join both substrates 1 and 54 to each other, to thereby provide an envelope, which is then evacuated to a high vacuum.
The cathode substrate 1 and anode substrate 54 are superposed on each other while being deviated from each other in an oblique direction and while being spaced from each other at a predetermined interval and are hermetically joined to each other by means of the seal material 4. In FIG. 7, the seal material 4 is arranged somewhat inside an outer contour of a superposed area between both substrates 1 and 54 and in a predetermined width. Actually, the seal material 4 is arranged so as to extend to the contour or a vicinity to the contour.
A region in the thus-formed envelope on which the anode electrode 55 is arranged functions as an image display region. In a left-side region of the cathode substrate 1 positioned outside the seal material 4 in FIG. 7, terminal sections of the cathode electrodes 51 are led out to form the cathode lead-out wirings C. Likewise, the gate electrodes 52 have terminal sections led out in an upper region of the cathode substrate 1 positioned outside the seal member 4 in FIG. 7, resulting in the gate lead-out wirings G. Further, in a right-side region of the anode substrate 54 positioned outside the seal material 4, the anode lead-out wirings A are formed so as to extend from the anode electrode 55. The cathode substrate 1 and anode substrate 54 are arranged so as to be spaced from each other at a reduced interval while being opposite to each other, so that it is physically substantially impossible to carry out both connection of the cathode substrate 1 to the drive circuit and that of the anode substrate 54 thereto at the same position. Thus, the respective lead-out wirings are formed so as to extend in directions different from each other as described above.
Expansion of the above-described monochrome FED permits a color FED of the primary colors to be realized, although it is not shown in FIG. 7 for the sake of brevity. More specifically, in this instance, a plurality of such anode electrodes 55 are arranged in a stripe-like manner in correspondence to luminous colors of phosphors for the primary colors and connected to a plurality of anode lead-out wirings different from each other, respectively.
Such a conventional Spindt type FED as described above may be constructed in such a manner as shown in FIG. 8 by way of example, which corresponds to a fragmentary sectional view taken along one of the gate electrodes in FIG. 7. In FIG. 8, reference numeral 57 designates emitters. The cathode substrate 1 made of glass or the like is provided thereon with the cathode electrodes 51, which are made of metal and arranged so as to extend in a direction perpendicular to the sheet of FIG. 8. Then, the insulating layer 2 formed of a silicon dioxide (SiO.sub.2) film or the like is deposited all over the cathode substrate 1 to cover the cathode electrodes 51. The insulating layer 2 is formed into a thickness of about 1 .mu.m.
Then, the gate electrodes 52 are formed into a thickness of about 0.2 .mu.m on the insulating layer 2 so as to extend in a direction perpendicular to the cathode electrodes 51. The apertures 53 formed so as to commonly extend through the gate electrode 52 and insulating layer 2 each have the emitter 57 of a conical shape arranged therein. The emitters 57 each are made of metal such as molybdenum or the like and formed on the cathode electrode 51. The emitters 57 each are exposed at a distal end thereof through the aperture 53 while being directed toward the anode electrode 55.
The emitters 57 are arranged at pitches of 10 .mu.m or less, so that tens of thousands to hundreds of thousands of such emitters may be arranged on one such cathode substrate 1. Also, the emitters 57 may be so arranged that a distance between the gate electrode 52 and the distal end of the emitter 57 is set to be as small as less than a micron, so that application of a voltage as low as tens of volts between the gate electrodes 52 and the emitters 57 permits electrons to be field-emitted from the emitters 57. Thus, in the conventional Spindt type FED, the cathode electrodes 51, emitters 57 and gate electrodes 52 cooperate with each other to provide an electrode source. Thus, when a positive voltage is kept applied to the anode electrode 55 shown in FIG. 6, the anode electrode 55 captures electrons emitted from the emitters 57, so that the phosphor provided on the anode electrode 55 emits light.
As described above with reference to FIG. 6, the cathode substrate 1 and anode substrate 54 are so arranged that an interval therebetween is kept at, for example, 0.2 mm, resulting in the envelope being provided and the insulating studs 56 and seal material 4 are arranged between the substrates 1 and 54 to form a high vacuum in the envelope. The gate electrodes 52 are required to be arranged both inside and outside the sealed portion of the envelope defined by the seal material 4, so that the seal material 4 is caused to be contacted with the gate electrodes 52.
FIGS. 9(A) and 9(B) each are a sectional view taken along line A--A of FIG. 8 showing a construction employed for solving the above-described problem of the FED shown in FIG. 8; wherein FIG. 9(A) shows the gate electrode in an ideal state and FIG. 9(B) shows it after a heat treatment.
In FIGS. 9(A) and 9(B), the gate electrodes 52 are conventionally made of niobium (Nb). In general, Nb is increased in adhesion to glass or the like, to thereby be readily used as compared with tungsten, so that a pattern of the gate electrodes 52 may be formed by dry etching. In this connection, the gate electrodes made of Nb should be inherently kept adhered onto the insulating layer 2 even after the heat treatment; however, heating of the gate electrodes 52 to a temperature of about 500.degree. C. causes the gate electrodes of the lead-out sections to be oxidized by the frit glass seal material used for hermetically sealing the envelope as shown in FIG. 9(B). This causes the gate electrodes 52 to be peeled from the insulating layer 2, resulting in the seal material 4 entering therebetween, leading to formation of a gap 58. The gap 58 thus formed causes a slow leak phenomenon which causes a vacuum in the envelope to be gradually reduced over a long period of time. Also, the oxidation leads to an increase in resistance of the gate electrodes 52 or breakage thereof, leading to a failure in conduction thereof.
FIG. 10 shows another manner in which the conventional Spindt type FED may be constructed. In the example of FIG. 10, the gate electrodes 52 each are formed on a portion thereof contacted with the seal material 4 with a protective film 61 for protecting the gate electrode 52. The protective film 61 is formed of silicon dioxide (SiO.sub.2) into a thickness of about 1 to 2 .mu.m. Such arrangement of the protective film 61 effectively prevents peeling of the gate electrode 52 from the insulating layer 2.
Unfortunately, pattern-formation of the protective film 61 on only the portion of the gate electrode 52 on which the seal material 4 is formed leads to an increase in the number of steps in manufacturing of the FED and complication of a manufacturing process thereof. More particularly, steps for formation of the protective film 61 and for patterning thereof are additionally required.